1. Field of the Invention
The present invention generally relates to resume events from Power-On Suspend mode, and more particularly to a method and apparatus for externally generating System Control Interrupts as resume events from Power-On Suspend mode.
2. Description of the Related Art
Since 1989, certain microprocessors, such as the Pentium(copyright) processor from Intel Corporation, have included a System Management Mode (SMM), which is entered upon receipt of a System Management Interrupt (SMI). SMM allows embedded code within the Basic Input Output System (BIOS) to slow down, suspend, or shut down part or all of the system platform, and even the Central Processing Unit (CPU) itself. SMIs were originally devised by Intel Corporation for portable systems. Portable computers often draw power from batteries which provide a limited amount of energy. To maximize battery life, an SMI is typically asserted to turn off or reduce the power to any system component not in use or to turn the power back on. Although originally designed for laptop computers, SMIs have become popular for desktop and other stationary computers as well, helping lower power usage.
In 1991, Intel and Microsoft Corporation introduced the Advanced Power Management (APM) specification as a means of integrating the operating system (OS) into the power management loop, allowing communication between the OS and the power management (PM) code embedded within the BIOS. APM creates an interface between the OS and the BIOS. One part of APM is the definition of four power states: full on, APM Enabled, APM Standby, and APM Suspend. In the APM Standby state, most devices are in a low power mode, the CPU clock is slowed or stopped, and the system is in a low power state which can be returned to normal activity quickly by events such as interrupts. No system context is lost. This state has become commonly known as Power-On Suspend (POS) mode.
Because developments in computer systems continued, the APM specification became inadequate to handle the changing hardware. One need was for a more general control of PM by the OS, which has access to more information about what tasks are running and what the user is doing, and is therefore in a better position to decide what devices should be on or off. The Advanced Configuration and Power Interface (ACPI) specification was developed in 1997 to address these needs, a copy of which is incorporated herein by reference.
On legacy (non-ACPI) systems, the SMI is an OS-transparent interrupt generated by interrupt events such as IRQs. By contrast, on ACPI systems, interrupt events generate an OS-visible system interrupt to notify the OS of ACPI events, known as a System Control Interrupt (SCI). Hardware platforms that support both legacy operating systems and ACPI systems must support a way of remapping the interrupt events between SMIs and SCIs when switching between ACPI and legacy models.
Controller chipsets which support both legacy and ACPI models exist. For example, the Silicon Integrated Systems Corporation""s SIS 5595 chipset allows an IRQ to directly cause an SCI resume event. However, certain otherwise desirable chipsets, such as the VIA VT82C586B, are very limited in what events can generate an SCI. In the case of the VT82C586B, for example, hardware interrupts (IRQs) are not events capable of generating an SCI and therefore are not events which can resume a computer from POS mode. These limited capabilities have rendered such chipsets unsuitable for certain computer systems.
Briefly, a computer system according to an embodiment of the present invention provides a processor, an interrupt generator coupled to the processor, a System Management Interrupt (SMI) generator to generate an SMI in response to the interrupt generator, and a controller coupled to the processor providing an input connected to the SMI generator and a POS resume event signal generator to receive the SMI and generate a POS resume event signal to resume the computer system from Power-On Suspend (POS) mode.
In one embodiment of the invention, the controller is incapable of directly generating the POS resume event signal in response to an interrupt.
In another embodiment of the invention, the controller is a PCI/ISA bridge, preferably a VIA VT82C586B.
In one embodiment of the invention, the input pin is a GPIO pin. In another embodiment of the invention, the interrupt is an IRQ. Preferably, the POS resume event signal is a System Control Interrupt (SCI).